Figure 286. Update Rate Examples Depending On Mode And Timx_Rcr Register Settings - ST STM32G4 Series Reference Manual

Advanced-control timers (TIM1/TIM8/TIM20)
In Center aligned mode, for odd values of RCR, the update event occurs either on the
overflow or on the underflow depending on when the RCR register was written and when
the counter was launched: if the RCR was written before launching the counter, the UEV
occurs on the overflow. If the RCR was written after launching the counter, the UEV occurs
on the underflow.
For example, for RCR = 3, the UEV is generated each 4th overflow or underflow event
depending on when the RCR was written.

Figure 286. Update rate examples depending on mode and TIMx_RCR register settings

Counter
TIMx_CNT
TIMx_RCR = 0
UEV
TIMx_RCR = 1
UEV
TIMx_RCR = 2
TIMx_RCR = 3
TIMx_RCR = 3
and
re-synchronization
UEV
Update event: Preload registers transferred to active registers and update interrupt generated
Update Event if the repetition counter underflow occurs when the counter is equal to the auto-reload value.
27.3.6 External trigger input
The timer features an external trigger input tim_etr_in. It can be used as:
•
external clock (external clock mode 2, see
•
trigger for the slave mode (see
•
PWM reset input for cycle-by-cycle current regulation (see
Figure 287
with the ETP bit in TIMxSMCR register. The trigger can be prescaled with the divider
programmed by the ETPS[1:0] bitfield and digitally filtered with the ETF[3:0] bitfield. The
resulting signal (tim_etrf) is available for three purposes: as an external clock, to condition
1062/2083
Counter-aligned mode
UEV
UEV
UEV
(by SW)
below describes the tim_etr_in input conditioning. The input polarity is defined
Upcounting
(by SW)
Section
Section 27.3.30)
RM0440 Rev 1
Edge-aligned mode
Downcounting
(by SW)
27.3.7)
Section 27.3.9)
RM0440
MSv31195V1