Figure 567. Rs232 Cts Flow Control - ST STM32G4 Series Reference Manual

Low-power universal asynchronous receiver transmitter (LPUART)
nCTS
Transmit data register
TDR
TX
Note: For correct behavior, nCTS must be asserted at least 3 LPUART clock source periods
before the end of the current character. In addition it should be noted that the CTSCF flag
may not be set for pulses shorter than 2 x PCLK periods.
RS485 driver enable
The driver enable feature is enabled by setting bit DEM in the LPUART_CR3 control
register. This allows activating the external transceiver control, through the DE (Driver
Enable) signal. The assertion time is the time between the activation of the DE signal and
the beginning of the start bit. It is programmed using the DEAT [4:0] bitfields in the
LPUART_CR1 control register. The de-assertion time is the time between the end of the last
stop bit, in a transmitted message, and the de-activation of the DE signal. It is programmed
using the DEDT [4:0] bitfields in the LPUART_CR1 control register. The polarity of the DE
signal can be configured using the DEP bit in the LPUART_CR3 control register.
The LPUART DEAT and DEDT are expressed in LPUART clock source (f
•
The Driver enable assertion time equals
–
–
•
The Driver enable de-assertion time equals
–
–
where P = BRR[20:11]
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Figure 567. RS232 CTS flow control

Data 2
Stop
Start
Data 1
bit
bit
Writing data 3 in TDR
(1 + (DEAT x P)) x f
CK
(1 + DEAT) x f , if P = 0
CK
(1 + (DEDT x P)) x f
CK
(1 + DEDT) x f , if P = 0
CK
empty Data 3
Data 2
Transmission of Data 3 is
delayed until nCTS = 0
, if P # 0
, if P # 0
RM0440 Rev 1
CTS CTS
Stop Start
Idle
bit bit
) cycles:
CK
RM0440
empty
Data 3
MSv31167V1