Table 136. Fmc_Bcrx Bit Fields; Figure 68. Synchronous Multiplexed Write Mode Waveforms - Psram (Cram) - ST STM32G4 Series Reference Manual

RM0440

Figure 68. Synchronous multiplexed write mode waveforms - PSRAM (CRAM)

HCLK
CLK
A[25:16]
NEx
Hi-Z
NOE
NWE
NADV
NWAIT
(WAITCFG = 0)
A/D[15:0]
1 clock 1 clock
1. The memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Bit number
31:24
23:22
20
19
18:16
15
14
13
Memory transaction = burst of 2 half words
addr[25:16]
(DATLAT + 2)
CLK cycles
Addr[15:0]

Table 136. FMC_BCRx bit fields

Bit name
Reserved 0x000
NBLSET[1:0] Don't care
CCLKEN As needed
CBURSTRW 0x1
CPSIZE As needed (0x1 for CRAM 1.5)
ASYNCWAIT 0x0
EXTMOD 0x0
To be set to 1 if the memory supports this feature, to be kept at 0
WAITEN
otherwise.
RM0440 Rev 1
Flexible memory controller (FMC)
inserted wait state
data
Value to set
data
ai14731f
507/2083
531