Flash Securable Area Bank2 Register (Flash_Sec2R) - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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Embedded Flash memory (FLASH) for category 3 devices

Bits 31:17 Reserved, must be kept cleared

Flash Securable area bank2 register (FLASH_SEC2R)

Address offset: 0x74

Reset value: 0xFFFF FFXX

Access: no wait state when no Flash memory operation is on going, word, half-word and

byte access.

Bit 16 BOOT_LOCK: Unique boot entry point.

When this bit is set, the boot is done from user flash only, whatever the RDP

level. This bit can be reset by SW only in level0. In level 1, the only way to reset

this bit is by doing a level regression (level 1 => level 0), which forces a mass

erase of the flash.

Bits 15:8 Reserved, must be kept cleared

Bit 7:0 SEC_SIZE1: sets the number of pages used in the bank 1 Securable memory

Securable area starts at @ 0x0800 0000 and its size is SEC_SIZE1 * page size.

This field can be changed in level0 only.

Any attempt to modify in level1 silently fails, and does not change register value.

Bits 31:8 Reserved, must be kept cleared

Bit 7:0 SEC_SIZE2: sets the number of pages used in the bank 2 Securable memory

Securable area starts at @ 0x0804 0000 and its size is SEC_SIZE2 * page size.

When DBANK=0, this field is not usefull.

This field can be changed in level0 only. Any attempt to modify in level1 silently

fails, and does change register value.

RM0440 Rev 1

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