ST STM32G4 Series Reference Manual page 996

High-resolution timer (HRTIM)
26.5.57 HRTIM output disable register (HRTIM_ODISR)
Address offset: 0x398
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 TF2ODIS: Timer F output 2 disable
Refer to TA1ODIS description.
Bit 10 TF1ODIS: Timer F output 1 disable
Refer to TA1ODIS description
Bit 9 TE2ODIS: Timer E output 2 disable
Refer to TA1ODIS description.
Bit 8 TE1ODIS: Timer E output 1 disable
Refer to TA1ODIS description.
Bit 7 TD2ODIS: Timer D output 2 disable
Refer to TA1ODIS description.
Bit 6 TD1ODIS: Timer D output 1 disable
Refer to TA1ODIS description.
Bit 5 TC2ODIS: Timer C output 2 disable
Refer to TA1ODIS description.
Bit 4 TC1ODIS: Timer C output 1 disable
Refer to TA1ODIS description.
Bit 3 TB2ODIS: Timer B output 2 disable
Refer to TA1ODIS description.
Bit 2 TB1ODIS: Timer B output 1 disable
Refer to TA1ODIS description.
Bit 1 TA2ODIS: Timer A output 2 disable
Refer to TA1ODIS description.
Bit 0 TA1ODIS: Timer A output 1 disable
Setting this bit disables the timer A output 1. The output enters the idle state, either from the run state
or from the fault state.
Writing "0" has no effect.
996/2083
28 27 26 25
Res. Res. Res.
12 11 10 9
TF2 TF1 TE2
ODIS ODIS ODIS
w w w
24 23 22
Res. Res. Res.
8 7 6
TE1 TD2 TD1
ODIS ODIS ODIS ODIS
w w w
RM0440 Rev 1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
TC2 TC1 TB2 TB1
ODIS ODIS ODIS
w w w w
RM0440
17 16
Res. Res.
1 0
TA2 TA1
OD OD
IS IS
w w