ST STM32G4 Series Reference Manual page 255

RM0440
Bit 5 PLLRDYF: PLL ready interrupt flag
Bit 4 HSERDYF: HSE ready interrupt flag
Bit 3 HSIRDYF: HSI16 ready interrupt flag
Bit 2 Reserved, must be kept at reset value.
Bit 1 LSERDYF: LSE ready interrupt flag
Bit 0 LSIRDYF: LSI ready interrupt flag
6.4.7 Clock interrupt clear register (RCC_CICR)
Address offset: 0x20
Reset value: 0x0000 0000
Access: no wait state, word, half-word and byte access
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Set by hardware when the PLL locks and PLLRDYDIE is set.
Cleared by software setting the PLLRDYC bit.
0: No clock ready interrupt caused by PLL lock
1: Clock ready interrupt caused by PLL lock
Set by hardware when the HSE clock becomes stable and HSERDYDIE is set.
Cleared by software setting the HSERDYC bit.
0: No clock ready interrupt caused by the HSE oscillator
1: Clock ready interrupt caused by the HSE oscillator
Set by hardware when the HSI16 clock becomes stable and HSIRDYDIE is set in a
response to setting the HSION (refer to
not set but the HSI16 oscillator is enabled by the peripheral through a clock request, this bit
is not set and no interrupt is generated.
Cleared by software setting the HSIRDYC bit.
0: No clock ready interrupt caused by the HSI16 oscillator
1: Clock ready interrupt caused by the HSI16 oscillator
Set by hardware when the LSE clock becomes stable and LSERDYDIE is set.
Cleared by software setting the LSERDYC bit.
0: No clock ready interrupt caused by the LSE oscillator
1: Clock ready interrupt caused by the LSE oscillator
Set by hardware when the LSI clock becomes stable and LSIRDYDIE is set.
Cleared by software setting the LSIRDYC bit.
0: No clock ready interrupt caused by the LSI oscillator
1: Clock ready interrupt caused by the LSI oscillator
28 27 26 25
Res. Res. Res.
12 11 10 9
HSI48 LSE
Res.
RDYC CSSC
w w
Clock control register
24 23 22
Res. Res. Res. Res.
8 7 6
CSSC Res. Res.
RDYC
w
RM0440 Rev 1
Reset and clock control (RCC)
(RCC_CR)). When HSION is
21 20 19 18
Res. Res. Res.
5 4 3 2
PLL HSE HSI
Res.
RDYC RDYC
w w w
17 16
Res. Res.
1 0
LSE LSI
RDYC RDYC
w w
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