Figure 428. Control Circuit In External Clock Mode 2 + Trigger Mode; Figure 429. Master/Slave Timer Example - ST STM32G4 Series Reference Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
tim_cnt_ck, tim_psc_ck
28.4.23 Timer synchronization
The TIMx timers are linked together internally for timer synchronization or chaining. When
one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of
another Timer configured in Slave Mode.
Figure 429: Master/Slave timer example
the master mode selection blocks.
Clock
Prescaler Counter
Using one timer as prescaler for another timer
For example, TIM_mstr can be configured to act as a prescaler for TIM_slv. Refer to
Figure 429. To do this:
1252/2083

Figure 428. Control circuit in external clock mode 2 + trigger mode

tim_ti1
CEN
ETR
Counter register
TIF

Figure 429. Master/Slave timer example

TIM_mstr
MMS
UEV
Master
tim_trgo
mode
control
34
presents an overview of the trigger selection and
TS
SMS
Slave
tim_itr
mode
control
Input
trigger
selection
RM0440 Rev 1
35
TIM_slv
CK_PSC
Prescaler
RM0440
36
MSv62364V1
Counter
MSv62375V1