ST STM32G4 Series Reference Manual page 676

Analog-to-digital converters (ADC)
Bit 16 ADRDY_SLV: Slave ADC ready
Bits 15:11 Reserved, must be kept at reset value.
Bit 10 JQOVF_MST: Injected Context Queue Overflow flag of the master ADC
Bit 9 AWD3_MST: Analog watchdog 3 flag of the master ADC
Bit 8 AWD2_MST: Analog watchdog 2 flag of the master ADC
Bit 7 AWD1_MST: Analog watchdog 1 flag of the master ADC
Bit 6 JEOS_MST: End of injected sequence flag of the master ADC
Bit 5 JEOC_MST: End of injected conversion flag of the master ADC
Bit 4 OVR_MST: Overrun flag of the master ADC
Bit 3 EOS_MST: End of regular sequence flag of the master ADC
Bit 2 EOC_MST: End of regular conversion of the master ADC
Bit 1 EOSMP_MST: End of Sampling phase flag of the master ADC
Bit 0 ADRDY_MST: Master ADC ready
20.7.2 ADC x common control register (ADCx_CCR) (x=1/2 or 3/4/5)
Address offset: 0x08 (this offset address is relative to the master ADC base address +
0x300)
Reset value: 0x0000 0000
One interface controls ADC1 and ADC2, while the other interface controls ADC3, ADC4 and
ADC5.
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
DMA
MDMA[1:0] Res.
CFG
rw rw rw
676/3748
This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.
This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register.
This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register.
This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register.
This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register.
This bit is a copy of the JEOS bit in the corresponding ADC_ISR register.
This bit is a copy of the JEOC bit in the corresponding ADC_ISR register.
This bit is a copy of the OVR bit in the corresponding ADC_ISR register.
This bit is a copy of the EOS bit in the corresponding ADC_ISR register.
This bit is a copy of the EOC bit in the corresponding ADC_ISR register.
This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register.
This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register.
27 26 25
Res. Res. Res.
11 10 9
DELAY[3:0]
rw rw rw
24 23 22
VBATS VSENSES VREF
EL EL EN
rw rw rw
8 7 6
Res. Res.
rw
RM0440 Rev 1
21 20 19 18
PRESC[3:0]
rw rw rw rw
5 4 3 2
Res. DUAL[4:0]
rw rw rw
RM0440
17 16
CKMODE[1:0]
rw rw
1 0
rw rw