Table 321. Processing Latency For Gcm And Ccm (In Clock Cycle) - ST STM32G4 Series Reference Manual

AES hardware accelerator (AES)

Table 321. Processing latency for GCM and CCM (in clock cycle)

Key size Mode of operation
Mode 1: Encryption/
128-bit
Mode 3: Decryption
Mode 1: Encryption/
256-bit
Mode 3: Decryption
Note: Data insertion can include wait states forced by AES on the AHB bus (maximum 3 cycles,
typical 1 cycle). This applies to all header/payload/tag phases
1484/2083
Algorithm Init Phase
GCM 64
CCM 63
GCM 88
CCM 87
RM0440 Rev 1
Header Payload
phase phase
35 51
55 114
35 75
79 162
RM0440
Tag phase
59
58
75
82