Table 171. Data Format (Case Of 12-Bit Data); Figure 155. Data Registers In Dual Dac Channel Mode - ST STM32G4 Series Reference Manual

RM0440
Depending on the loaded DAC_DHRyyyD register, the data written by the user is shifted
and stored into DHR1 and DHR2 (data holding registers, which are internal non-memory-
mapped registers). The DHR1 and DHR2 registers are then loaded into the DAC_DOR1
and DOR2 registers, respectively, either automatically, by software trigger or by an external
event trigger.
Signed/unsigned data
DAC input data are unsigned: 0x000 corresponds to the minimum value and 0xFFF to the
maximum value for 12-bit mode.
The DAC can also handle signed input data in 2's complement format. This is done by
setting SINFORMATx bit in the DAC_MCR register.
When SINFORMATx bit is set, the MSB bit of the data written to DHRx registers is inverted
when it is copied to the DAC_DORx register, and the DAC interface can accept signed data
(Q1.15, Q1.11 or Q1.7 format). DAC_DHR12Lx register can be used to store 16-bit signed
data in the data holding registers. The 12 MSBs of 16-bit data are used for the DAC output
data and the MSB bit is inverted. The four LSBs are simply ignored.
SINFORMATx bit

Figure 155. Data registers in dual DAC channel mode

31 24

Table 171. Data format (case of 12-bit data)

DATA written to DHRx
0
0
1
1
1
1
RM0440 Rev 1
Digital-to-analog converter (DAC)
15 7
DATA transfered to DORx register
register
0x000
0xFFF
0x7FF
0x000
0xFFF
0x800
0
8-bit right aligned
12-bit left aligned
12-bit right aligned
0x000
0xFFF
0xFFF
0x800
0x7FF
0x000
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