ST STM32G4 Series Reference Manual page 971

RM0440
26.5.39 HRTIM timer x chopper register (HRTIM_CHPxR) (x = A to F)
Address offset: Block A: 0x0D8
Address offset: Block B: 0x158
Address offset: Block C: 0x1D8
Address offset: Block D: 0x258
Address offset: Block E: 0x2D8
Address offset: Block F: 0x358
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res. Res. Res.
Bits 31:11 Reserved, must be kept at reset value.
Bits 10:7 STRPW[3:0]: Timer x start pulsewidth
This register defines the initial pulsewidth following a rising edge on output signal.
This bitfield cannot be modified when one of the CHPx bits is set.
t = (STRPW[3:0]+1) x 16 x t
1STPW
0000: 94.1 ns (1/10.625 MHz)
...
1111: 1.51 µs (16/10.625 MHz)
Bits 6:4 CARDTY[2:0]: Timer x chopper duty cycle value
This register defines the duty cycle of the carrier signal. This bitfield cannot be modified when one of
the CHPx bits is set.
000: 0/8 (i.e. only 1st pulse is present)
...
111: 7/8
Bits 3:0 CARFRQ[3:0]: Timer x carrier frequency value
This register defines the carrier frequency F
This bitfield cannot be modified when one of the CHPx bits is set.
0000: 10.625 MHz (f
...
1111: 664.1 kHz (f
28 27 26 25
Res. Res. Res.
12 11 10 9
Res. STRTPW[3:0]
rw rw
/ 16)
HRTIM
/ 256)
HRTIM
24 23 22
Res. Res. Res.
8 7 6
CARDTY[2:0 )
rw rw rw
.
HRTIM
= f
CHPFRQ HRTIM
RM0440 Rev 1
High-resolution timer (HRTIM)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
CARFRQ[3:0]
rw rw rw rw
/ (16 x (CARFRQ[3:0]+1)).
17 16
Res. Res.
1 0
rw rw
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