Figure 129. Triggered Regular Oversampling Mode (Trovs Bit = 1) - ST STM32G4 Series Reference Manual

Analog-to-digital converters (ADC)
If the TROVS bit is set, the content of the DISCEN bit is ignored and considered as 1.
CONT=0
DISCEN = 1
TROVS = 0
CONT=0
DISCEN = 1
TROVS = 1
Injected and regular sequencer management when oversampling
In oversampling mode, it is possible to have differentiated behavior for injected and regular
sequencers. The oversampling can be enabled for both sequencers with some limitations if
they have to be used simultaneously (this is related to a unique accumulation unit).
Oversampling regular channels only
The regular oversampling mode bit ROVSM defines how the regular oversampling
sequence is resumed if it is interrupted by injected conversion:
•
In continued mode, the accumulation restarts from the last valid data (prior to the
conversion abort request due to the injected trigger). This ensures that oversampling
will be completed whatever the injection frequency (providing at least one regular
conversion can be completed between triggers);
•
In resumed mode, the accumulation restarts from 0 (previous conversions results are
ignored). This mode allows to guarantee that all data used for oversampling were
converted back-to-back within a single timeslot. Care must be taken to have a injection
trigger period above the oversampling period length. If this condition is not respected,
the oversampling cannot be completed and the regular sequencer will be blocked.
The Figure 130
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Figure 129. Triggered regular oversampling mode (TROVS bit = 1)

Trigger
Ch(N) Ch(N)
0
Trigger Trigger
Ch(N) Ch(N)
0
gives examples for a 4x oversampling ratio.
Ch(N) Ch(N)
1 2 3
EOC flag set
Trigger Trigger
Ch(N) Ch(N)
1 2
RM0440 Rev 1
Trigger
Ch(N) Ch(N) Ch(N)
0 1
Trigger Trigger
Ch(N) Ch(N)
3 0 1
EOC flag set
RM0440
Ch(N)
2 3
Trigger
Ch(N)
2
MS34455V2