Table 164. Delay Bits Versus Adc Resolution - ST STM32G4 Series Reference Manual

Analog-to-digital converters (ADC)
Bits 15:14 MDMA[1:0]: Direct memory access mode for dual ADC mode
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 13 DMACFG: DMA configuration (for dual ADC mode)
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 12 Reserved, must be kept at reset value.
Bits 11:8 DELAY: Delay between 2 sampling phases
Note: The software is allowed to write these bits only when the ADCs are disabled
Bits 7:5 Reserved, must be kept at reset value.
Bits 4:0 DUAL[4:0]: Dual ADC mode selection
Note: The software is allowed to write these bits only when the ADCs are disabled
DELAY bits
0000
0001
0010
678/3748
This bitfield is set and cleared by software. Refer to the DMA controller section for more
details.
00: MDMA mode disabled
01: Reserved
10: MDMA mode enabled for 12 and 10-bit resolution
11: MDMA mode enabled for 8 and 6-bit resolution
no regular conversion is ongoing).
This bit is set and cleared by software to select between two DMA modes of operation and is
effective only when DMAEN=1.
0: DMA One Shot mode selected
1: DMA Circular mode selected
For more details, refer to
no regular conversion is ongoing).
These bits are set and cleared by software. These bits are used in dual interleaved modes.
Refer to Table 164 for the value of ADC resolution versus DELAY bits values.
(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).
These bits are written by software to select the operating mode.
All the ADCs independent:
00000: Independent mode
00001 to 01001: Dual mode, master and slave ADCs working together
00001: Combined regular simultaneous + injected simultaneous mode
00010: Combined regular simultaneous + alternate trigger mode
00011: Combined Interleaved mode + injected simultaneous mode
00100: Reserved
00101: Injected simultaneous mode only
00110: Regular simultaneous mode only
00111: Interleaved mode only
01001: Alternate trigger mode only
All other combinations are reserved and must not be programmed
(ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0).

Table 164. DELAY bits versus ADC resolution

12-bit resolution
1 * T
adc_ker_ck
2 * T
adc_ker_ck
3 * T
adc_ker_ck
Section : Managing conversions using the DMA
10-bit resolution
1 * T
adc_ker_ck
2 * T
adc_ker_ck
3 * T
adc_ker_ck
RM0440 Rev 1
8-bit resolution 6-bit resolution
1 * T 1 * T
adc_ker_ck
2 * T 2 * T
adc_ker_ck
3 * T 3 * T
adc_ker_ck
RM0440
adc_ker_ck
adc_ker_ck
adc_ker_ck