ST STM32G4 Series Reference Manual page 771

RM0440
24.5.6 OPAMP6 control/status register (OPAMPx_CSR) (x = 1...6)
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29
CAL
LOCK Res.
OUT
rw r
15 14 13
PGA_GAIN CALSEL
rw rw rw
Bit 31 LOCK: OPAMP6_CSR lock
This bit is write-once. It is set by software. It can only be cleared by a system reset.
This bit is used to configure the OPAMP6_CSR register as read-only.
0: OPAMP6_CSR is read-write
1: OPAMP6_CSR is read-only
Bit 30 CALOUT: Operational amplifier calibration output
This bit shows the digital value of OPAMP output and is the calibration output status during
calibration offset mode (Calibration is successful when CALOUT switches from 1 to 0.)
Bit 29 Reserved, must be kept at reset value.
Bits 28:24 TRIMOFFSETN [4:0]: Trim for NMOS differential pairs
Bits 23:19 TRIMOFFSETP [4:0]: Trim for PMOS differential pairs
At reset these bits are loaded by the factory trimming value. They can be modified only when
USER_TRIM =1
28 27 26 25
TRIMOFFSETN
rw rw rw rw
12 11 10 9
CALON Res. Res.
rw rw
24 23 22 21
TRIMOFFSETP
rw rw rw rw
8 7 6
OPA OPA
VM_SEL
INTOEN HSM
rw rw rw rw
RM0440 Rev 1
Operational amplifiers (OPAMP)
20 19 18
rw rw rw
5 4 3 2
USER
VP_SEL
TRIM.
rw rw
17 16
PGA_GAIN
rw rw
1 0
FORCE
OPAEN
_VP
rw rw
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