ST STM32G4 Series Reference Manual page 200

Power control (PWR)
5. Some peripherals with wakeup from Stop capability can request HSI16 to be enabled. In this case, HSI16 is woken up by
the peripheral, and only feeds the peripheral which requested it. HSI16 is automatically put off when the peripheral does not
need it anymore.
6. UART and LPUART reception is functional in Stop mode, and generates a wakeup interrupt on Start, address match or
received frame event.
7. I2C address detection is functional in Stop mode, and generates a wakeup interrupt in case of address match.
8. Voltage scaling Range 1 only.
9. I/Os can be configured with internal pull-up, pull-down or floating in Standby mode.
10. The I/Os with wakeup from Standby/Shutdown capability are: PA0, PC13, PE6, PA2, PC5.
11. I/Os can be configured with internal pull-up, pull-down or floating in Shutdown mode but the configuration is lost when
exiting the Shutdown mode.
Debug mode
By default, the debug connection is lost if the application puts the MCU in Stop 0, Stop1,
Standby or Shutdown mode while the debug features are used. This is due to the fact that
the Cortex
However, by setting some configuration bits in the DBGMCU_CR register, the software can
be debugged even when using the low-power modes extensively. For more details, refer to
Section 1.16.1: Debug support for low-power
5.3.1 Run mode
Slowing down system clocks
In Run mode, the speed of the system clocks (SYSCLK, HCLK, PCLK) can be reduced by
programming the prescaler registers. These prescalers can also be used to slow down the
peripherals before entering the Sleep mode.
For more details, refer to
Peripheral clock gating
In Run mode, the HCLK and PCLK for individual peripherals and memories can be stopped
at any time to reduce the power consumption.
To further reduce the power consumption in Sleep mode, the peripheral clocks can be
disabled prior to executing the WFI or WFE instructions.
The peripheral clock gating is controlled by the RCC_AHBxENR and RCC_APBxENR
registers.
Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting
the corresponding bit in the RCC_AHBxSMENR and RCC_APBxSMENR registers.
5.3.2 Low-power run mode (LP run)
To further reduce the consumption when the system is in Run mode, the regulator can be
configured in low-power mode. In this mode, the CPU frequency should not exceed 2 MHz.
Please refer to the product datasheet for more details on voltage regulator and peripherals
operating conditions.
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®
-M4 with FPU core is no longer clocked.
Section 1.4.3: Clock configuration register
modes.
RM0440 Rev 1
RM0440
(RCC_CFGR).