ST STM32G4 Series Reference Manual page 674

Analog-to-digital converters (ADC)
Bits 31:23 Reserved, must be kept at reset value.
Bits 22:16 CALFACT_D[6:0]: Calibration Factors in differential mode
These bits are written by hardware or by software.
Once a differential inputs calibration is complete, they are updated by hardware with the calibration
factors.
Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it will then be applied once a new differential
calibration is launched.
Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0
(ADC is enabled and no calibration is ongoing and no conversion is ongoing).
Bits 15:7 Reserved, must be kept at reset value.
Bits 6:0 CALFACT_S[6:0]: Calibration Factors In single-ended mode
These bits are written by hardware or by software.
Once a single-ended inputs calibration is complete, they are updated by hardware with the
calibration factors.
Software can write these bits with a new calibration factor. If the new calibration factor is different
from the current one stored into the analog ADC, it will then be applied once a new single-ended
calibration is launched.
Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0
(ADC is enabled and no calibration is ongoing and no conversion is ongoing).
20.6.23 ADC Gain compensation Register (ADC_GCOMP)
Address offset: 0xC0
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
Res. Res.
rw
Bits 31:14 Reserved, must be kept at reset value.
Bits 13:0 GCOMPCOEFF[13:0]: Gain compensation coefficient
These bits are set and cleared by software to program the gain compensation coefficient.
00 1000 0000 0000: gain factor of 0.5
...
01 0000 0000 0000: gain factor of 1
10 0000 0000 0000: gain factor of 2
11 0000 0000 0000: gain factor of 3
...
The coefficient is divided by 4096 to get the gain factor ranging from 0 to 3.999756.
Note: This gain compensation is only applied when GCOMP bit of ADC_CFGR2 register is 1.
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28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
GCOMPCOEFF[13:0]
rw rw rw
RM0440 Rev 1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
RM0440
17 16
Res. Res.
1 0
rw rw