FD controller area network (FDCAN)
fdcan_clk
CFG_APB
fdcan1_intr0_it
fdcan1_intr1_it
Ctrl_APB
fdcan_pclk
fdcan1_ts[0:15]
RAM_APB
1902/2083
Figure 661. CAN subsystem
/ 1..30
Sub system
CKDIV
Config reg
Interrupts
interface
Control and
Configuration
Tx Req
registers
Message RAM
interface
RAM
Controller / Arbiter
RM0440 Rev 1
Configuration
fdcan_tq_ck
CAN core
Sync
Tx State Rx State
TX Handler
TX prioritization
Frame Synchro
RX Handler
Acceptance filter
CANFDL
CANFDL
CANFDL
Message RAM
Buffers
FIFOs
Filters
RM0440
FDCAN_RX1
FDCAN_TX1
FDCAN_RX2
FDCAN_TX2
FDCAN_RX3
FDCAN_TX3
APB clock domain
Kernel clock domain
MS51818V1
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