Table 293. Tim15 Register Map And Reset Values - ST STM32G4 Series Reference Manual

General-purpose timers (TIM15/TIM16/TIM17)
Bits 31:0 DMAB[31:0]: DMA register for burst accesses
A read or write operation to the DMAR register accesses the register located at the address
where TIM15_CR1 address is the address of the control register 1, DBA is the DMA base
address configured in TIM15_DCR register, DMA index is automatically controlled by the
DMA transfer, and ranges from 0 to DBL (DBL configured in TIM15_DCR).
29.7.23 TIM15 register map
TIM15 registers are mapped as 16-bit addressable registers as described in the table
below:
Register
Offset
name
TIM15_CR1
0x00
Reset value
TIM15_CR2
0x04
Reset value
TIM15_SMCR
0x08
Reset value
TIM15_DIER
0x0C
Reset value
TIM15_SR
0x10
Reset value
TIM15_EGR
0x14
Reset value
TIM15_CCMR1
Input Capture
mode
Reset value
0x18
TIM15_CCMR1
Output
Compare mode
Reset value
1372/2083
(TIM15_CR1 address) + (DBA + DMA index) x 4

Table 293. TIM15 register map and reset values

TS
[4:3]
0 0
0
RM0440 Rev 1
CKD
[1:0]
0 0
0 0
0
0 0 0 0
0 0
IC2
CC2S
IC2F[3:0] PSC
[1:0]
[1:0]
0 0 0 0 0 0 0
OC2M CC2S
[2:0] [1:0]
0 0 0 0 0 0 0 0
RM0440
0 0 0 0 0
MMS[2:0]
0 0 0 0 0 0 0
TS[2:0] SMS[2:0]
0 0 0 0 0 0
0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
IC1
CC1S
IC1F[3:0] PSC
[1:0]
[1:0]
0 0 0 0 0 0 0 0
OC1M CC1S
[2:0] [1:0]
0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0