ST STM32G4 Series Reference Manual page 274

Reset and clock control (RCC)
Bit 15 SPI4EN: SPI4 timer clock enable
Set and cleared by software.
0: SPI4 timer clock disabled
1: SPI4 timer clock enabled
Bit 14 USART1EN: USART1clock enable
Set and cleared by software.
0: USART1clock disabled
1: USART1clock enabled
Bit 13 TIM8EN: TIM8 timer clock enable
Set and cleared by software.
0: TIM8 timer clock disabled
1: TIM8 timer clock enabled
Bit 12 SPI1EN: SPI1 clock enable
Set and cleared by software.
0: SPI1 clock disabled
1: SPI1 clock enabled
Bit 11 TIM1EN: TIM1 timer clock enable
Set and cleared by software.
0: TIM1 timer clock disabled
1: TIM1P timer clock enabled
Bits 10:1 Reserved, must be kept at reset value.
Bit 0 SYSCFGEN: SYSCFG + COMP + VREFBUF + OPAMP clock enable
Set and cleared by software.
0: SYSCFG + COMP + VREFBUF + OPAMP clock disabled
1: SYSCFG + COMP + VREFBUF + OPAMP clock enabled
6.4.20 AHB1 peripheral clocks enable in Sleep and Stop modes register
(RCC_AHB1SMENR)
Address offset: 0x68
Access: no wait state, word, half-word and byte access
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
CRCSM
Res. Res. Res.
EN
rw
274/2083
Reset value: 0x0000 130F
27 26 25 24
Res. Res. Res. Res.
11 10 9 8
SRAM1 FLASH
Res. Res.
SMEN SMEN
rw rw
RM0440 Rev 1
23 22 21 20
Res. Res. Res. Res.
7 6 5 4
FMACSM
Res. Res. Res.
EN
rw
19 18 17
Res. Res. Res.
3 2 1
CORDICSM DMAMUX1 DMA2
EN SMEN SMEN
rw rw rw
RM0440
16
Res.
0
DMA1
SMEN
rw