Table 359. Clock Generator Programming Examples - ST STM32G4 Series Reference Manual

Serial audio interface (SAI)
Clock generator programming examples
Table 359
Input
sai_x_ker_ck MCLK F
clock frequency
Y
98.304 MHz
N
1. N is an integer value between 3 and 8.
39.3.9 Internal FIFOs
Each audio block in the SAI has its own FIFO. Depending if the block is defined to be a
transmitter or a receiver, the FIFO can be written or read, respectively. There is therefore
only one FIFO request linked to FREQ bit in the SAI_xSR register.
An interrupt is generated if FREQIE bit is enabled in the SAI_xIM register. This depends on:
•
FIFO threshold setting (FLVL bits in SAI_xCR2)
•
Communication direction (transmitter or receiver). Refer to
transmitter mode
Interrupt generation in transmitter mode
The interrupt generation depends on the FIFO configuration in transmitter mode:
• When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO empty
(FTH[2:0] set to 0b000), an interrupt is generated (FREQ bit set by hardware to 1 in
SAI_xSR register) if no data are available in SAI_xDR register (FLVL[2:0] bits in SAI_xSR
is less than 001b). This Interrupt (FREQ bit in SAI_xSR register) is cleared by hardware
when the FIFO is no more empty (FLVL[2:0] bits in SAI_xSR are different from 0b000) i.e
one or more data are stored in the FIFO.
• When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO quarter full
(FTH[2:0] set to 001b), an interrupt is generated (FREQ bit set by hardware to 1 in
SAI_xSR register) if less than a quarter of the FIFO contains data (FLVL[2:0] bits in
SAI_xSR are less than 0b010). This Interrupt (FREQ bit in SAI_xSR register) is cleared
by hardware when at least a quarter of the FIFO contains data (FLVL[2:0] bits in SAI_xSR
are higher or equal to 0b010).
• When the FIFO threshold bits in SAI_xCR2 register are configured as FIFO half full
(FTH[2:0] set to 0b010), an interrupt is generated (FREQ bit set by hardware to 1 in
1764/2083
gives programming examples for 48, 96 and 192 kHz.

Table 359. Clock generator programming examples

(1)
/ F FRL
MCLK FS
N
512 2 -1
N
512 2 -1
N
512 2 -1
N
256 2 -1
N
256 2 -1
N
256 2 -1
- 63
- 63
- 63
and Interrupt generation in reception
OSR NODIV MCKEN
1 0 1
1 0 1
1 0 1
0 0 1
0 0 1
0 0 1
- 1 0
- 1 0
- 1 0
RM0440 Rev 1
Audio Sampling
MCKDIV[5:0]
frequency (F
0 or 1 192 kHz
2 96 kHz
4 48 kHz
2 192 kHz
4 96 kHz
8 48 kHz
8 192 kHz
16 96 kHz
32 48 kHz
Interrupt generation in
mode.
RM0440
)
FS