ST STM32G4 Series Reference Manual page 516

Flexible memory controller (FMC)
Bits 15:8 DATAST[7:0]: Data-phase duration.
These bits are written by software to define the duration of the data phase (refer to
Figure
0000 0000: Reserved
0000 0001: DATAST phase duration = 1 × HCLK clock cycles
0000 0010: DATAST phase duration = 2 × HCLK clock cycles
...
1111 1111: DATAST phase duration = 255 × HCLK clock cycles (default value after reset)
Bits 7:4 ADDHLD[3:0]: Address-hold phase duration.
These bits are written by software to define the duration of the address hold phase (refer to
Figure 60
0000: Reserved
0001: ADDHLD phase duration = 1 × HCLK clock cycle
0010: ADDHLD phase duration = 2 × HCLK clock cycle
...
1111: ADDHLD phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always
1 Flash clock period duration.
Bits 3:0 ADDSET[3:0]: Address setup phase duration.
These bits are written by software to define the duration of the address setup phase in HCLK
cycles (refer to
0000: ADDSET phase duration = 0 × HCLK clock cycle
...
1111: ADDSET phase duration = 15 × HCLK clock cycles (default value after reset)
Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash
clock period duration. In muxed mode, the minimum ADDSET value is 1.
PSRAM chip select counter register (FMC_PCSCNTR)
Address offset: 0x20
Reset value: 0x0000 0000
This register contains the PSRAM chip select counter value for Synchronous and
Asynchronous modes. The chip select counter is common to all banks and can be enabled
separately on each bank. During PSRAM read or write accesses, this value is loaded into a
timer which is decremented while the NE signal is held low. When the timer reaches 0, the
PSRAM controller splits the current access, toggles NE to allow PSRAM device refresh, and
restarts a new access. The programmed counter value guarantees a maximum NE pulse
width (t
CEM
decrementing each time a new access is started by a transition of NE from high to low.
h
31 30
Res. Res.
15 14
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516/2083
63), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:
to Figure 63), used in asynchronous multiplexed accesses:
Figure 51 to Figure
) as specified for PSRAM devices. The counter is reloaded and starts
29 28 27
Res. Res. Res. Res.
13 12 11
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63), used in asynchronous accesses:
26 25 24 23
Res. Res. Res.
10 9 8 7
CSCOUNT[15:0]
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RM0440 Rev 1
22 21 20 19
Res. Res. Res.
rw
6 5 4 3
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RM0440
Figure 51 to
18 17 16
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2 1 0
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