Table 310. Lptim Register Map And Reset Values - ST STM32G4 Series Reference Manual

Low-power timer (LPTIM)
31.7.10 LPTIM register map
The following table summarizes the LPTIM registers.
Offset Register name
LPTIM_ISR
0x000
Reset value
LPTIM_ICR
0x004
Reset value
LPTIM_IER
0x008
Reset value
LPTIM_CFGR
0x00C
Reset value
LPTIM_CR
0x010
Reset value
LPTIM_CMP
0x014
Reset value
LPTIM_ARR
0x018
Reset value
LPTIM_CNT
0x01C
Reset value
LPTIM_OR
0x020
Reset value
1. If LPTIM does not support encoder mode feature, this bit is reserved. Please refer to
implementation.
1440/2083

Table 310. LPTIM register map and reset values

0 0 0 0 0 0 0 0 0
RM0440 Rev 1
0 0 0 0 0 0 0 0
CMP[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ARR[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
CNT[15:0]
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Section 31.3: LPTIM
RM0440
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 0