ST STM32G4 Series Reference Manual page 416

Advanced arm-based 32-bit mcus

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Extended interrupts and events controller (EXTI)

Falling trigger selection register 2 (EXTI_FTSR2)

Address offset: 0x2C

Reset value: 0x0000 0000

Bits 31:10 Reserved, must be kept at reset value.

The configurable wakeup lines are edge-triggered. No glitch must be generated on these

lines. If a falling edge on a configurable interrupt line occurs during a write operation to the

EXTI_FTSR register, the pending bit is not set.

Rising and falling edge triggers can be set for the same interrupt line. In this case, both

generate a trigger condition.

Software interrupt event register 2 (EXTI_SWIER2)

Address offset: 0x30

Reset value: 0x0000 0000

Bits 9:8 FTx: Falling trigger event configuration bit of line x (x = 40 to 41)

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line

Bits 7:2 Reserved, must be kept at reset value.

Bits 1:0 FTx: Falling trigger event configuration bit of line x (x = 32 to 33)

0: Falling trigger disabled (for Event and Interrupt) for input line

1: Falling trigger enabled (for Event and Interrupt) for input line

RM0440 Rev 1

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