ST STM32G4 Series Reference Manual page 659

RM0440
Bits 31:28 Reserved, must be kept at reset value.
Bit 27 SMPTRIG: Sampling time control trigger mode
This bit is set and cleared by software to enable the sampling time control trigger mode.
0: Sampling time control trigger mode disabled
1: Sampling time control trigger mode enabled
The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge.
EXTEN bit should be set to 01. BULB bit must not be set when the SMPTRIG bit is set.
When EXTEN bit is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the
conversion.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 26 BULB: Bulb sampling mode
This bit is set and cleared by software to enable the bulb sampling mode.
0: Bulb sampling mode disabled
1: Bulb sampling mode enabled. The sampling period starts just after the previous end of
conversion.
SAMPTRIG bit must not be set when the BULB bit is set.
The very first ADC conversion is performed with the sampling time specified in SMPx bits.
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bit 25 SWTRIG: Software trigger bit for sampling time control trigger mode
This bit is set and cleared by software to enable the bulb sampling mode.
0: Software trigger starts the conversion for sampling time control trigger mode
1: Software trigger starts the sampling for sampling time control trigger mode
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 24:17 Reserved, must be kept at reset value.
Bit 16 GCOMP: Gain compensation mode
This bit is set and cleared by software to enable the gain compensation mode.
0: Regular ADC operating mode
1: Gain compensation enabled and applied on all channels
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
Bits 15:11 Reserved, must be kept at reset value.
Bit 10 ROVSM: Regular Oversampling mode
This bit is set and cleared by software to select the regular oversampling mode.
0: Continued mode: When injected conversions are triggered, the oversampling is temporary
stopped and continued after the injection sequence (oversampling buffer is maintained during
injected sequence)
1: Resumed mode: When injected conversions are triggered, the current oversampling is aborted
and resumed from start after the injection sequence (oversampling buffer is zeroed by injected
sequence start)
Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no
conversion is ongoing).
RM0440 Rev 1
Analog-to-digital converters (ADC)
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