Table 145. Quadspi Interrupt Requests - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus
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RM0440
19.4
QUADSPI interrupts
An interrupt can be produced on the following events:
Timeout
Status match
FIFO threshold
Transfer complete
Transfer error
Separate interrupt enable bits are available for flexibility.
Interrupt event
Timeout
Status match
FIFO threshold
Transfer complete
Transfer error

Table 145. QUADSPI interrupt requests

Event flag
TOF
SMF
FTF
TCF
TEF
RM0440 Rev 1
Quad-SPI interface (QUADSPI)
Enable control bit
TOIE
SMIE
FTIE
TCIE
TEIE
547/2083
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