ST STM32G4 Series Reference Manual page 931

RM0440
Bit 4 RETRIG: Re-triggerable mode
This bit defines the counter behavior in single shot mode.
0: The timer is not re-triggerable: a counter reset is done if the counter is stopped (period elapsed in
single-shot mode or counter stopped in continuous mode)
1: The timer is re-triggerable: a counter reset is done whatever the counter state.
Bit 3 CONT: Continuous mode
This bit defines the timer operating mode.
0: The timer operates in single-shot mode and stops when it reaches TIMxPER value
1: The timer operates in continuous mode and rolls over to zero when it reaches TIMxPER value
Bits 2:0 CKPSCx[2:0]: HRTIM timer x clock prescaler
These bits define the master timer high-resolution clock prescaler ratio.
The counter clock equivalent frequency (f
The prescaling ratio cannot be modified once the timer is enabled.
) is equal to f
COUNTER
RM0440 Rev 1
High-resolution timer (HRTIM)
CKPSC[2:0]
/ 2 .
HRCK
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