Figure 334. Index Generation For Ipos[1:0] = 11 - ST STM32G4 Series Reference Manual

RM0440
state combination) the index must be synchronized, using the IPOS[1:0] bitfield in the
TIMx_ECR register.
The Index detection event will act differently depending on counting direction to ensure
symmetrical operation during speed reversal:
•
The counter is reset during up-counting (DIR bit = 0).
•
The counter is set to TIMx_ARR when down counting.
This allows the index to be generated on the very same mechanical angular position
whatever the counting direction. The
generated, for a simplistic example (an encoder providing 4 edges par mechanical rotation).
The Figure 335
shows that the instant at which the counter value is forced is automatically adjusted
depending on the counting direction:
•
Counter set to 0 when encoder state is '11' (ChA=1, ChB=1), when up-counting (DIR bit
= 0).
•
Counter set to TIMx_ARR when exiting the '11' state, when down-counting (DIR bit =
1).
An interrupt can be issued upon index detection event.
The arrows are indicating on which transition is the index event interrupt generated.

Figure 334. Index generation for IPOS[1:0] = 11

Rotor angle = 270°
AB = 10
State 4
Rotor angle = 180°
The index event is always generated here
below presents waveforms and corresponding values for IPOS[1:0] = 11. It
Advanced-control timers (TIM1/TIM8/TIM20)
Figure 334 below shows at which position is the index
AB = 00
State 1
Up-counting
Down-counting
AB = 11
State 3
RM0440 Rev 1
Rotor angle = 0°
AB = 01
State 2
Rotor angle = 90°
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