ST STM32G4 Series Reference Manual page 666

Analog-to-digital converters (ADC)
Bits 22:18 SQ8[4:0]: 8th conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 17 Reserved, must be kept at reset value.
Bits 16:12 SQ7[4:0]: 7th conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 11 Reserved, must be kept at reset value.
Bits 10:6 SQ6[4:0]: 6th conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 5 Reserved, must be kept at reset value.
Bits 4:0 SQ5[4:0]: 5th conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
20.6.13 ADC regular sequence register 3 (ADC_SQR3)
Address offset: 0x38
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
SQ12[3:0]
rw rw rw
Bits 31:29 Reserved, must be kept at reset value.
Bits 28:24 SQ14[4:0]: 14th conversion in regular sequence
Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that
Bit 23 Reserved, must be kept at reset value.
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These bits are written by software with the channel number (0..18) assigned as the 8th in the
regular conversion sequence
no regular conversion is ongoing).
These bits are written by software with the channel number (0..18) assigned as the 7th in the
regular conversion sequence.
no regular conversion is ongoing).
These bits are written by software with the channel number (0..18) assigned as the 6th in the
regular conversion sequence.
no regular conversion is ongoing).
These bits are written by software with the channel number (0..18) assigned as the 5th in the
regular conversion sequence.
no regular conversion is ongoing).
28 27 26 25
SQ14[4:0]
rw rw rw rw
12 11 10 9
Res.
rw rw rw
These bits are written by software with the channel number (0..18) assigned as the 14th in
the regular conversion sequence.
no regular conversion is ongoing).
24 23 22
Res.
rw rw
8 7 6
SQ11[4:0]
rw rw rw
RM0440 Rev 1
21 20 19 18
SQ13[4:0]
rw rw rw rw
5 4 3 2
Res. SQ10[4:0]
rw rw rw
RM0440
17 16
Res. SQ12[4]
rw
1 0
rw rw