Figure 662. Fdcan Block Diagram - ST STM32G4 Series Reference Manual

FD controller area network (FDCAN)
43.3 FDCAN functional description
fdcan_intr0_it
fdcan_intr1_it
fdcan_pclk
fdcan_ts[0:15]
Dual interrupt lines
The FDCAN peripheral provides two interrupt lines, fdcan_intr0_it and fdcan_intr1_it.
By programming EINT0 and EINT1 bits in FDCAN_ILE register, the interrupt lines can be
separately enabled or disabled.
CAN core
The CAN core contains the Protocol Controller and receive / transmit shift registers. It
handles all ISO 11898-1: 2015 protocol functions and supports both 11-bit and 29-bit
identifiers.
Sync
The Sync block synchronizes signals from the APB clock domain to the CAN kernel clock
domain and vice versa.
1904/2083

Figure 662. FDCAN block diagram

Interrupts
interface
Control and
Ctrl_APB
Configuration
registers
Message RAM
interface
Kernel clock domain
fdcan_tq_ck
CAN core
Sync
Tx Req
Tx State Rx State
TX Handler
TX prioritization
Frame Synchro
RX Handler
Acceptance filter
RM0440 Rev 1
FDCAN_RX
FDCAN_TX
CANFDL
APB clock domain
RM0440
MS51819V1