ST STM32G4 Series Reference Manual page 946

High-resolution timer (HRTIM)
26.5.23 HRTIM timer x compare 4 register (HRTIM_CMP4xR) (x = A to F)
Address offset: Block A: 0x0AC
Address offset: Block B: 0x12C
Address offset: Block C: 0x1AC
Address offset: Block D: 0x22C
Address offset: Block E: 0x2AC
Address offset: Block F: 0x32C
Reset value: 0x0000 0000
31 30 29
Res. Res. Res. Res.
15 14 13
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 CMP4x[15:0]: Timer x compare 4 value
This register holds the compare 4 value.
This register holds either the content of the preload register or the content of the active register if
preload is disabled.
The compare value must be above or equal to 3 periods of the
CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
This register can behave as an auto-delayed compare register, if enabled with DELCMP4[1:0] bits in
HRTIM_TIMxCR.
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28 27 26 25
Res. Res. Res.
12 11 10 9
rw rw rw rw
24 23 22
Res. Res. Res.
8 7 6
CMP4x[15:0]
rw rw rw
RM0440 Rev 1
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
rw rw rw rw
f
clock, that is 0x60 if
HRTIM
RM0440
17 16
Res. Res.
1 0
rw rw