ST STM32G4 Series Reference Manual page 466

Advanced arm-based 32-bit mcus

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Filter Math Accelerator (FMAC)

FMAC registers

FMAC X1 Buffer Configuration register (FMAC_X1BUFCFG)

Address offset: 0x00

Reset value: 0x0000 0000

This register can only be modified if START = 0 in the FMAC_PARAM register.

Bits 31:26 Reserved

Bits 25:24 FULL_WM: Watermark for buffer full flag. Defines the threshold for setting the X1 buffer full

flag when operating in circular mode. The flag will be set if the number of free spaces in the

buffer is less than 2

Setting a threshold greater than 1 allows several data to be transferred into the buffer under

one interrupt.

Threshold should be set to 1 if DMA write requests are enabled (DMAWEN = 1 in FMAC_CR

Bits 23:16 Reserved

Bits 15:8 X1_BUF_SIZE: Allocated size of X1 buffer in 16-bit words

The minimum buffer size is the number of feed-forward taps in the filter (+ the watermark

threshold - 1).

Bits 7:0 X1_BASE: Base address of X1 buffer

FMAC X2 Buffer Configuration register (FMAC_X2BUFCFG)

Address offset: 0x04

Reset value: 0x0000 0000

0: Threshold = 1

1: Threshold = 2

2: Threshold = 4

3: Threshold = 8

RM0440 Rev 1

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