Read Access Latency - ST STM32G4 Series Reference Manual

Embedded Flash memory (FLASH) for category 3 devices
Single bank mode (DBANK=0, 128-bits data width)
Data in Flash memory are 144-bits words: 8 bits are added per each double word. The ECC
mechanism supports:
•
One error detection and correction
•
Two errors detection per 64 double words
The user must first check the SYSF_ECC bit, and if it is set, the user must refer to the
DBANK=1 programming model (because system Flash is always on 2 banks). If the bit is
not set, the user must refer to the following programing model:
Each double word (bits 63:0 and bits 127:64) has ECC.
When one error is detected in 64 LSB bits (bits 63:0) and corrected, a flag ECCC (ECC
correction) is set in the FLASH_ECCR register.
When one error is detected in 64 MSB bits (bits 127:64) and corrected, a flag ECCC2
(ECC2 correction) is set in the FLASH_ECCR register.
If the ECCCIE is set, an interrupt is generated. The user has to read ECCC and ECCC2 to
see which part of the 128-bits data has been corrected (either 63:0, 127:64 or both).
When two errors are detected in 64 LSB bits, a flag ECCD (ECC detection) is set in the
FLASH_ECCR register.
When two errors are detected in 64 MSB bits (bits 127:64), a flag ECCD2 (ECC2 detection)
is set in the FLASH_ECCR register.
In this case, a NMI is generated. The user has to read ECCD and ECCD2 to see which part
of the 128-bits data has error detection (either 63:0, 127:64 or both).
When an ECC error is detected, the address of the failing the 2 times double word is saved
into ADDR_ECC[20:0] in FLASH_ECCR. ADDR_ECC[20:0] contains an address of a 2
times double word.
The ADDR_ECC[3:0] are always cleared. BK_ECC is not used in this mode.
When ECCC/ECCC2 or ECCD/ECCD2 is/are set, if a new ECC error occurs, the
ADDR_ECC is not updated. The FLASH_ECCR is updated only if the ECC flags
(ECCC/ECCC2/ECCD/ECCD2) are cleared.
Note: For a virgin data: 0xFF FFFF FFFF FFFF FFFF, one error is detected and corrected but two
errors detection is not supported.
When an ECC error is reported, a new read at the failing address may not generate an ECC
error if the data is still present in the current buffer, even if ECCC and ECCD are cleared.
3.3.3

Read access latency

To correctly read data from Flash memory, the number of wait states (LATENCY) must be
correctly programmed in the
frequency of the CPU clock (HCLK) and the internal voltage range of the device V
Refer to
correspondence between wait states and CPU clock frequency.
94/2083
Flash access control register (FLASH_ACR)
Section 5.1.9: Dynamic voltage scaling management.
RM0440 Rev 1
RM0440
according to the
CORE
Table 19 shows the
.