Figure 560. Lpuart_Ker_Ck Clock Divider Block Diagram - ST STM32G4 Series Reference Manual

RM0440
Note: The ORE bit, when set, indicates that at least 1 data has been lost. T
When the FIFO mode is disabled, there are two possibilities
•
if RXNE=1, then the last valid data is stored in the receive register (RDR) and can be
read,
•
if RXNE=0, then the last valid data has already been read and there is nothing left to be
read in the RDR. This case can occur when the last valid data is read in the RDR at the
same time as the new (and lost) data is received.
Selecting the clock source
The choice of the clock source is done through the Clock Control system (see Section Reset
and clock controller (RCC)). The clock source must be selected through the UE bit, before
enabling the LPUART.
The clock source must be selected according to two criteria:
•
Possible use of the LPUART in low-power mode
• Communication speed.
The clock source frequency is lpuart_ker_ck.
When the dual clock domain and the wakeup from low-power mode features are supported,
the lpuart_ker_ck clock source can be configured in the RCC (see Section Reset and clock
controller (RCC)). Otherwise, the lpuart_ker_ck is the same as lpuart_pclk.
The lpuart_ker_ck can be divided by a programmable factor in the LPUART_PRESC
register.
lpuart_ker_ck
Some lpuart_ker_ck sources allow the LPUART to receive data while the MCU is in low-
power mode. Depending on the received data and wakeup mode selection, the LPUART
wakes up the MCU, when needed, in order to transfer the received data by software reading
the LPUART_RDR register or by DMA.
For the other clock sources, the system must be active to allow LPUART communications.
The communication speed range (specially the maximum communication speed) is also
determined by the clock source.
The receiver samples each incoming baud as close as possible to the middle of the baud-
period. Only a single sample is taken of each of the incoming bauds.
Note: There is no noise detection for data.
Low-power universal asynchronous receiver transmitter (LPUART)

Figure 560. lpuart_ker_ck clock divider block diagram

LPUARTx_PRESC[3:0]
RM0440 Rev 1
lpuart_ker_ck_pres
LPUARTx_BRR
oversampling
register and
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