ST STM32G4 Series Reference Manual page 722

Digital-to-analog converter (DAC)
21.7.12 DAC channel1 data output register (DAC_DOR1)
Address offset: 0x2C
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 DACC1DORB[11:0]: DAC channel1 data output
These bits are read-only. They contain data output for DAC channel1 B.
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DACC1DOR[11:0]: DAC channel1 data output
These bits are read-only, they contain data output for DAC channel1.
21.7.13 DAC channel2 data output register (DAC_DOR2)
This register is available only on dual-channel DACs. Refer to
implementation.
Address offset: 0x30
Reset value: 0x0000 0000
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:16 DACC2DORB[11:0]: DAC channel2 data output
Bits 15:12 Reserved, must be kept at reset value.
Bits 11:0 DACC2DOR[11:0]: DAC channel2 data output
722/2083
27 26 25
r r r
11 10 9
r r r
27 26 25
r r r
11 10 9
r r r
These bits are read-only. They contain data output for DAC channel2 B.
These bits are read-only, they contain data output for DAC channel2.
24 23 22
DACC1DORB[11:0]
r r r
8 7 6
DACC1DOR[11:0]
r r r
24 23 22
DACC2DORB[11:0]
r r r
8 7 6
DACC2DOR[11:0]
r r r
RM0440 Rev 1
21 20 19 18
r r r r
5 4 3 2
r r r r
Section 21.3: DAC
21 20 19 18
r r r r
5 4 3 2
r r r r
RM0440
17 16
r r
1 0
r r
17 16
r r
1 0
r r