Table 351. Stm32G4 Series Spi And Spi/I2S Implementation - ST STM32G4 Series Reference Manual

Serial peripheral interface / inter-IC sound (SPI/I2S)
38.3 I2S main features
• Half-duplex communication (only transmitter or receiver)
•
Master or slave operations
• 8-bit programmable linear prescaler to reach accurate audio sample frequencies (from
8 kHz to 192 kHz)
•
Data format may be 16-bit, 24-bit or 32-bit
•
Packet frame is fixed to 16-bit (16-bit data frame) or 32-bit (16-bit, 24-bit, 32-bit data
frame) by audio channel
•
Programmable clock polarity (steady state)
•
Underrun flag in slave transmission mode, overrun flag in reception mode (master and
slave) and Frame Error Flag in reception and transmitter mode (slave only)
• 16-bit register for transmission and reception with one data register for both channel
sides
•
Supported I
–
–
–
–
•
Data direction is always MSB first
•
DMA capability for transmission and reception (16-bit wide)
•
Master clock can be output to drive an external audio component. Ratio is fixed at
256 × F
38.4 SPI/I2S implementation
The following table describes all the SPI instances and their features embedded in the
devices.
Enhanced NSSP & TI modes
Hardware CRC calculation
I2S support
Data size configurable
Rx/Tx FIFO size
Wakeup capability from Low-power Sleep
1694/2083
2
S protocols:
2
I S Philips standard
MSB-justified standard (left-justified)
LSB-justified standard (right-justified)
PCM standard (with short and long frame synchronization on 16-bit channel frame
or 16-bit data frame extended to 32-bit channel frame)
(where F is the audio sampling frequency)
S S

Table 351. STM32G4 Series SPI and SPI/I2S implementation

SPI features SPI1
Yes
Yes
No
from 4 to 16- from 4 to 16-
bit
32-bit
Yes
RM0440 Rev 1
SPI2S2 SPI2S3
Yes Yes
Yes Yes
Yes Yes
from 4 to 16-
bit bit
32-bit 32-bit
Yes Yes
RM0440
SPI4
Yes
Yes
No
from 4 to 16-
bit
32-bit
Yes