Table 197. Rng Internal Input/Output Signals; Figure 176. Rng Block Diagram - ST STM32G4 Series Reference Manual

RM0440
25.3 RNG functional description
25.3.1 RNG block diagram
Figure 176
rng_it
rng_clk
25.3.2 RNG internal signals
Table 197
at the STM32 product level (on pads).
Signal name
shows the RNG block diagram.

Figure 176. RNG block diagram

Banked Registers
control
data
AHB
interface
status
AHB clock domain
RNG clock domain
describes a list of useful-to-know internal signals available at the RNG level, not

Table 197. RNG internal input/output signals

Signal type
rng_it Digital output
rng_hclk Digital input
rng_clk Digital input
True random number generator (RNG)
RNG_CR
RNG_DR
RNG_SR
Fault detection
Clock checker
en_osc
RNG global interrupt request
AHB clock
RNG dedicated clock, asynchronous to rng_hclk
RM0440 Rev 1
True RNG
Conditioning logic
128-bit
Raw data shift reg
2-bit
Sampling &
Normalization (x 2)
Analog Analog
noise noise
source 1 source 2
Analog noise source
Description
MSv42097V2
789/2083
800