I-Bus; D-Bus; Figure 1. System Architecture - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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System and memory overview

I-bus

This bus connects the instruction bus of the Cortex

This bus is used by the core to fetch instructions. The target of this bus is a memory

containing code (either internal Flash memory, internal SRAMs or external memories

through the FMC or QUADSPI).

This bus connects the data bus of the Cortex

is used by the core for literal load and debug access. The target of this bus is a memory

containing code (either internal Flash memory, internal SRAMs or external memories

through the FMC or QUADSPI).

-M4 with FPU core to the BusMatrix.

-M4 with FPU core to the BusMatrix. This bus

RM0440 Rev 1

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