Figure 66. Wait Configuration Waveforms - ST STM32G4 Series Reference Manual

Flexible memory controller (FMC)
The FMC supports both NOR Flash wait state configurations, for each chip select, thanks to
the WAITCFG bit in the FMC_BCRx registers (x = 0..3).
A[25:16]
NWAIT
(WAITCFG = 0)
NWAIT
(WAITCFG = 1)
A/D[15:0]
504/2083

Figure 66. Wait configuration waveforms

HCLK
CLK
addr[25:16]
NADV
addr[15:0]
Memory transaction = burst of 4 half words
data data
RM0440 Rev 1
inserted wait state
data
RM0440
ai15798c