Figure 444. Counter Timing Diagram, Update Event When Arpe=1; (Timx_Arr Preloaded) - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus

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Counter register

Counter overflow

Update event (UEV)

Update interrupt flag

Auto-reload preload

Auto-reload shadow

Write a new value in TIMx_ARR

Repetition counter

Section 29.4.3: Time-base unit

respect to the counter overflows. It is actually generated only when the repetition counter

has reached zero. This can be useful when generating PWM signals.

This means that data are transferred from the preload registers to the shadow registers

(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx

capture/compare registers in compare mode) every N counter overflows, where N is the

value in the TIMx_RCR repetition counter register.

The repetition counter is decremented at each counter overflow.

The repetition counter is an auto-reload type; the repetition rate is maintained as defined by

the TIMx_RCR register value (refer to

software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave

mode controller, it occurs immediately whatever the value of the repetition counter is and the

repetition counter is reloaded with the content of the TIMx_RCR register.

Figure 444. Counter timing diagram, update event when ARPE=1

describes how the update event (UEV) is generated with

General-purpose timers (TIM15/TIM16/TIM17)

445). When the update event is generated by

RM0440 Rev 1

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