Figure 285. Counter Timing Diagram, Update Event With Arpe=1 (Counter Overflow) - ST STM32G4 Series Reference Manual

RM0440

Figure 285. Counter timing diagram, Update event with ARPE=1 (counter overflow)

Counter register
Counter overflow
Update event (UEV)
Update interrupt flag
Auto-reload preload
Auto-reload active
27.3.5 Repetition counter
Section 27.3.3: Time-base unit
respect to the counter overflows/underflows. It is actually generated only when the repetition
counter has reached zero. This can be useful when generating PWM signals.
This means that data are transferred from the preload registers to the shadow registers
(TIMx_ARR auto-reload register, TIMx_PSC prescaler register, but also TIMx_CCRx
capture/compare registers in compare mode) every N+1 counter overflows or underflows,
where N is the value in the TIMx_RCR repetition counter register.
The repetition counter is decremented:
• At each counter overflow in upcounting mode,
•
At each counter underflow in downcounting mode,
• At each counter overflow and at each counter underflow in center-aligned mode.
Although this limits the maximum number of repetition to 32768 PWM cycles, it makes
it possible to update the duty cycle twice per PWM period. When refreshing compare
registers only once per PWM period in center-aligned mode, maximum resolution is
2xT
The repetition counter is an auto-reload type; the repetition rate is maintained as defined by
the TIMx_RCR register value (refer to
software (by setting the UG bit in TIMx_EGR register) or by hardware through the slave
mode controller, it occurs immediately whatever the value of the repetition counter is and the
repetition counter is reloaded with the content of the TIMx_RCR register.
tim_psc_ck
CEN
tim_cnt_ck
F7
(UIF)
FD
register
Write a new value in TIMx_ARR
register
, due to the symmetry of the pattern.
ck
Advanced-control timers (TIM1/TIM8/TIM20)
F8 F9 FA FB FC
FD
describes how the update event (UEV) is generated with
Figure 286). When the update event is generated by
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