Table 120. Fmc_Bcrx Bit Fields; Figure 54. Modea Write Access Waveforms - ST STM32G4 Series Reference Manual

Flexible memory controller (FMC)
A[25:0]
NBL[x:0]
NEx
NOE
NWE
Data bus
The differences compared with Mode1 are the toggling of NOE and the independent read
and write timings.
Bit number
31:24
23:22
20
19
18:16
15
14
13
12
11
10
9
8
7
6
5:4
488/2083

Figure 54. ModeA write access waveforms

NBLSET ADDSET HCLK cycles
HCLK
cycles

Table 120. FMC_BCRx bit fields

Bit name
Reserved 0x000
NBLSET[1:0] As needed
CCLKEN As needed
CBURSTRW 0x0 (no effect in Asynchronous mode)
CPSIZE 0x0 (no effect in Asynchronous mode)
ASYNCWAIT Set to 1 if the memory supports this feature. Otherwise keep at 0.
EXTMOD 0x1
WAITEN 0x0 (no effect in Asynchronous mode)
WREN As needed
WAITCFG Don't care
Reserved 0x0
WAITPOL Meaningful only if bit 15 is 1
BURSTEN 0x0
Reserved 0x1
FACCEN Don't care
MWID As needed
RM0440 Rev 1
Memory transaction
Data driven by controller
DATAST HCLK cycles
Value to set
RM0440
DATAHLD +1
HCLK cycles
MSv41665V1