Flash Control Register (Flash_Cr) - ST STM32G4 Series Reference Manual

RM0440
4.7.6

Flash control register (FLASH_CR)

Address offset: 0x14
Reset value: 0xC000 0000
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
31 30 29 28
OPT SEC_
LOCK Res.
LOCK PROT1
rs rs rs
15 14 13 12
Res. Res. Res. Res.
Embedded Flash memory (FLASH) for category 2 devices
Bit 6 SIZERR: Size error
Set by hardware when the size of the access is a byte or half-word during a
program or a fast program sequence. Only double word programming is allowed
(consequently: word access).
Cleared by writing 1.
Bit 5 PGAERR: Programming alignment error
Set by hardware when the data to program cannot be contained in the same 64-
bit Flash memory row in case of standard programming, or if there is a change of
page during fast programming.
Cleared by writing 1.
Bit 4 WRPERR: Write protection error
Set by hardware when an address to be erased/programmed belongs to a write-
protected part (by WRP, PCROP or RDP level 1) of the Flash memory.
Cleared by writing 1.
Bit 3 PROGERR: Programming error
Set by hardware when a double-word address to be programmed contains a
value different from '0xFFFF FFFF' before programming, except if the data to
write is '0x0000 0000'.
Cleared by writing 1.
Bit 2 Reserved, must be kept at reset value.
Bit 1 OPERR: Operation error
Set by hardware when a Flash memory operation (program / erase) completes
unsuccessfully.
This bit is set only if error interrupts are enabled (ERRIE = 1).
Cleared by writing '1'.
Bit 0 EOP: End of operation
Set by hardware when one or more Flash memory operation (programming /
erase) has been completed successfully.
This bit is set only if the end of operation interrupts are enabled (EOPIE = 1).
Cleared by writing 1.
27 26 25
OBL_ RD ERR
LAUNCH ERRIE IE
rc_w1 rw rw
11 10 9
Res. Res.
rw
RM0440 Rev 1
24 23 22 21
EOP
Res. Res. Res.
IE
rw
8 7 6 5
PNB[6:0]
rw rw rw rw
20 19 18 17
OPT
Res. Res. FSTPG
STRT
rw rs
4 3 2 1
MER1 PER
rw rw rw rw
16
STRT
rs
0
PG
rw
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