Figure 417. Directional Index Sensitivity; Figure 418. Counter Reset As Function Of Fidx Bit Setting - ST STM32G4 Series Reference Manual

General-purpose timers (TIM2/TIM3/TIM4/TIM5)
Index input
IDIR[1:0]=00
IDIR[1:0]=01
IDIR[1:0]=10
Special first index event management
The FIDX bit in the TIMx_ECR register allows the Index to be taken only once, as shown on
the Figure 418
ignored. If needed, the circuitry can be re-armed by writing the FIDX bit to 0 and setting it
again to 1.
Note: When FIDX = 1, the index can be issued twice (IDXF flag set) if the direction changes at
position 0 (index active).
Index input
1242/2083

Figure 417. Directional index sensitivity

DIR bit UP-counting
Counter
below. Once the first index has arrived, any subsequent index will be

Figure 418. Counter reset as function of FIDX bit setting

Counter
FIDX = 0
FIDX = 1
RM0440 Rev 1
RM0440
Down-counting
MSv45774V1
MSv45775V1