Flash Option Register (Flash_Optr) - ST STM32G4 Series Reference Manual

Embedded Flash memory (FLASH) for category 2 devices
Bits 29:25 Reserved, must be kept at reset value.
Bits 21:19 Reserved, must be kept at reset value.
Bits 18:0 ADDR_ECC: ECC fail address
4.7.8

Flash option register (FLASH_OPTR)

Address offset: 0x20
Reset value: 0xFXXX XXXX. Register bits are loaded with values from Flash memory at
OBL.
Access: no wait state when no Flash memory operation is on going, word, half-word and
byte access
31 30 29
NRST_MODE
Res. IRHEN
[1:0]
rw rw
15 14 13
nRST_ nRST_ nRST_
Res.
SHDW STDBY STOP
rw rw
178/2083
Bit 31 ECCD: ECC detection
Set by hardware when two ECC errors have been detected (only if ECCC/ECCD
are previously cleared). When this bit is set, a NMI is generated.
Cleared by writing 1.
Bit 30 ECCC: ECC correction
Set by hardware when one ECC error has been detected and corrected (only if
ECCC/ECCC2/ECCD/ECCD2 are previously cleared). An interrupt is generated
if ECCCIE is set.
Cleared by writing 1.
Bit 24 ECCCIE: ECC correction interrupt enable
0: ECCC interrupt disabled
1: ECCC interrupt enabled.
This bit enables the interrupt generation when the ECCC bit in the FLASH_ECCR
register is set.
Bit 23 Reserved, must be kept at reset value.
Bit 22 SYSF_ECC: System Flash ECC fail
This bit indicates that the ECC error correction or double ECC error detection is
located in the System Flash.
This bit indicates which address in the Flash memory is concerned by the ECC
error correction or by the double ECC error detection.
28 27 26 25
CCM
n nSW
SRAM_
BOOT0 BOOT0
RST
rw rw rw rw
12 11 10 9
Res. BOR_LEV[2:0]
rw rw rw
24 23 22
SRAM nBOOT
Res.
_PE 1
rw rw
8 7 6
rw rw rw
RM0440 Rev 1
21 20 19 18
WWDG IWGD_
Res. Res.
_SW STDBY
rw rw
5 4 3 2
RDP[7:0]
rw rw rw rw
RM0440
17 16
IWDG_
IWDG_
SW
StOP
rw rw
1 0
rw rw