Figure 451. Output Stage Of Capture/Compare Channel (Channel 1); Figure 452. Output Stage Of Capture/Compare Channel (Channel 2 For Tim15) - ST STM32G4 Series Reference Manual

General-purpose timers (TIM15/TIM16/TIM17)

Figure 451. Output stage of capture/compare channel (channel 1)

tim_oc1ref
CNT>CCR1
Output
mode
CNT=CCR1
controller
tim_oc2ref
OC1CE OC1M[3:0]
TIMx_CCMR1

Figure 452. Output stage of capture/compare channel (channel 2 for TIM15)

CNT > CCR2
CNT = CCR2
The capture/compare block is made of one preload register and one shadow register. Write
and read always access the preload register.
In capture mode, captures are actually done in the shadow register, which is copied into the
preload register.
In compare mode, the content of the preload register is copied into the shadow register
which is compared to the counter.
29.4.8 Input capture mode
In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the
value of the counter after a transition detected by the corresponding tim_icx signal. When a
capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or
a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was
1316/2083
To the master mode
controller
tim_oc1refc
Output Dead-time
selector generator
DTG[7:0]
TIMx_BDTR
tim_oc2ref
Output
mode
controller
tim_oc1ref
OC2CE OC2M[3:0]
TIMx_CCMR2
'0'
x0
01
tim_oc1_dt
11
tim_oc1n_dt
11
10
'0'
0x
CC1NE CC1E
TIMx_CCER
To the master
mode controller
tim_oc2refc
'0'
0
Output
1
selector
CC2E
TIMx_CCER
RM0440 Rev 1
0
Output
enable
1
circuit
CC1P
TIMx_CCER
0
Output
enable
1
circuit
CC1E TIMx_CCER
CC1NE
CC1NP MOE OSSI OSSR
TIMx_BDTR
TIMx_CCER
OIS1 OIS1N
TIMx_CR2
0
Output
enable
1
circuit
CC2P
CC2E TIMx_CCER
TIMx_CCER
OIS2 TIMx_CR2
RM0440
tim_oc1
tim_oc1n
MSv62366V1
tim_oc2
MSv62367V1