Figure 276. Counter Timing Diagram, Internal Clock Divided By 2; Figure 277. Counter Timing Diagram, Internal Clock Divided By 4 - ST STM32G4 Series Reference Manual

Advanced arm-based 32-bit mcus
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RM0440
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag
Counter register
Counter underflow
Update event (UEV)
Update interrupt flag

Figure 276. Counter timing diagram, internal clock divided by 2

tim_psc_ck
CEN
tim_cnt_ck
0002
(UIF)

Figure 277. Counter timing diagram, internal clock divided by 4

tim_psc_ck
CEN
tim_cnt_ck
0001
(UIF)
Advanced-control timers (TIM1/TIM8/TIM20)
0000
0001
0000
RM0440 Rev 1
0036
0034
0035
0000
0033
MSv62306V1
0001
MSv62307V1
1055/2083
1181

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