Table 317. Dma Channel Configuration For Memory-To-Aes Data Transfer; Figure 524. Dma Transfer Of A 128-Bit Data Block During Input Phase - ST STM32G4 Series Reference Manual

AES hardware accelerator (AES)

Table 317. DMA channel configuration for memory-to-AES data transfer

DMA channel control
register field
Transfer size
Source burst size
(memory)
Destination burst size
(peripheral)
DMA FIFO size
Source transfer width
(memory)
Destination transfer
width (peripheral)
Source address
increment (memory)
Destination address
increment (peripheral)
Note: According to the algorithm and the mode selected, special padding / ciphertext stealing
might be required. For example, in case of AES GCM encryption or AES CCM decryption, a
DMA transfer must not include the last block. Refer to
perform a cipher operation

Figure 524. DMA transfer of a 128-bit data block during input phase

Word3
DIN[127:96]
D127
MSB
DMA
DMA req N
single write
1
(No swapping)
1
I127
MSB
1 4
Order of write to AES_DINR
1480/2083
Message length: a multiple of 128 bits.
According to the algorithm and the mode selected, special padding/
ciphertext stealing might be required. For example, in case of AES GCM
encryption or AES CCM decryption, a DMA transfer must not include the
last block. Refer to
operation for details.
Single
Single
AES FIFO_size = 4 bytes.
32-bit words
32-bit words
Yes, after each 32-bit transfer
Fixed address of AES_DINR (no increment)
for details.
Chronological order
Increasing address
Memory accessed through DMA
Word2
DIN[95:64]
D96 D95
DMA
DMA req N+1
single write
2
2
AES core input buffer
I96 I95
Recommended configuration
Section 33.4.4: AES procedure to perform a cipher
Word1
DIN[63:32]
D64 D63
DMA
DMA req N+2
single write
3
AES_DINR
3
I64 I63
RM0440 Rev 1
Section 33.4.4: AES procedure to
Word0
DIN[31:0]
D32 D31
DMA
DMA req N+3
single write
4
4
I32 I31
RM0440
D0
LSB
I0
LSB
MSv42160V1