ST STM32G4 Series Reference Manual page 60

List of figures
Figure 146. Two Interleaved channels (CH1, CH2) with injected sequence CH11, CH12
- case 2: Slave interrupted first . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
Figure 147. DMA Requests in regular simultaneous mode when MDMA=0b00 . . . . . . . . . . . . . . . . . 639
Figure 148. DMA requests in regular simultaneous mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . 640
Figure 149. DMA requests in interleaved mode when MDMA=0b10 . . . . . . . . . . . . . . . . . . . . . . . . . . 640
Figure 150. Temperature sensor channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
Figure 151. VBAT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643
Figure 152. VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
Figure 153. Dual-channel DAC block diagram
Figure 154. Data registers in single DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688
Figure 155. Data registers in dual DAC channel mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689
Figure 156. Timing diagram for conversion with trigger disabled TEN = 0 . . . . . . . . . . . . . . . . . . . . . 690
Figure 157. DAC LFSR register calculation algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
Figure 158. DAC conversion (SW trigger enabled) with LFSR wave generation. . . . . . . . . . . . . . . . . 699
Figure 159. DAC triangle wave generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700
Figure 160. DAC conversion (SW trigger enabled) with triangle wave generation . . . . . . . . . . . . . . . 700
Figure 161. DAC sawtooth wave generation (STDIRx=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Figure 162. DAC sawtooth wave generation (STDIRx=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
Figure 163. DAC sawtooth STINCTRIG and STRSTTRIG priority (STDIR = 0) . . . . . . . . . . . . . . . . . 702
Figure 164. DAC Sample and Hold mode phase diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704
Figure 165. Comparator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736
Figure 166. Comparator hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Figure 167. Comparator output blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
Figure 168. Standalone mode: external gain setting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747
Figure 169. Follower configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748
Figure 170. PGA mode, internal gain setting (x2/x4/x8/x16/x32/x64),
inverting input not used. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749
Figure 171. PGA mode, internal gain setting (x2/x4/x8/x16/x32/x64),
inverting input used for filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
Figure 172. PGA mode, non-inverting gain setting (x2/x4/x8/x16/x32/x64)
or inverting gain setting (x-1/x-3/x-7/x-15/x-31/x-63) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
Figure 173. PGA mode, non-inverting gain setting (x2/x4/x8/x16/x32/x64)
or inverting gain setting (x-1/x-3/x-7/x-15/x-31/x-63) with filtering . . . . . . . . . . . . . . . . . . 752
Figure 174. Example configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
Figure 175. Timer controlled Multiplexer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755
Figure 176. RNG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789
Figure 177. Entropy source model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790
Figure 178. RNG initialization overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793
Figure 179. High-resolution timer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804
Figure 180. Counter and capture register format vs clock prescaling factor . . . . . . . . . . . . . . . . . . . . 810
Figure 181. Timer A..F overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812
Figure 182. Continuous timer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
Figure 183. Single-shot timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
Figure 184. Timer reset resynchronization (prescaling ratio above 32) . . . . . . . . . . . . . . . . . . . . . . . . 816
Figure 185. Repetition rate versus HRTIM_REPxR content in continuous mode . . . . . . . . . . . . . . . . 817
Figure 186. Repetition counter behavior in single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
Figure 187. Compare events action on outputs: set on compare 1, reset on compare 2 . . . . . . . . . . 819
Figure 188. Timer A timing unit capture circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823
Figure 189. Auto-delayed overview (compare 2 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
Figure 190. Auto-delayed compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
Figure 191. Triggered-half mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
Figure 192. Push-pull mode block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
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RM0440 Rev 1
RM0440