ST STM32G4 Series Reference Manual page 876

High-resolution timer (HRTIM)
start or timer A start), a pulse is sent on the HRTIM_SCOUT output when exiting the burst
mode.
Note: TxBM bit must not be set when the balanced idle mode is active (DLYPRT[1:0] = 0x11).
Burst mode clock
The burst mode controller counter can be clocked by several sources, selected with
BMCLK[3:0] bits in the HRTIM_BMCR register:
•
BMCLK[3:0] = 0000 to 0101: master timer and TIMA..E reset/roll-over events. This
allows to have burst mode idle and run periods aligned with the timing unit counting
period (both in free-running and counter reset mode).
•
BMCLK[3:0] = 0110 to 1001: The clocking is provided by the hrtim_bm_ck[4:1] inputs
connected to general purpose timers, as in
and run periods are not necessarily aligned with timing unit counting period (a pulse on
the output may be interrupted, resulting a waveform with modified duty cycle for
instance.
•
BMCLK[3:0] = 1010: The f
bits in HRTIM_BMCR register. In this case, the burst mode idle and run periods are not
necessarily aligned with the timing unit counting period (a pulse on the output may be
interrupted, resulting in a waveform with a modified duty cycle, for instance.
The pulse width on TIMx OC output must be at least N f
detected by the HRTIM burst mode controller.
Burst mode triggers
To trigger the burst operation, 32 sources are available and are selected using the
HRTIM_BMTRGR register:
• Software trigger (set by software and reset by hardware)
•
6 master timer events: repetition, reset/roll-over, compare 1 to 4
• 5 x 4 events from timers A..F: repetition, reset/roll-over, compare 1 and 2
•
External event 7 (including TIMA event filtering) and 8 (including TIMD event filtering)
• Timer A period following external event 7 (including TIMA event filtering)
•
Timer D period following external event 8 (including TIMD event filtering)
• An on-chip event on the hrtim_bm_trg input (connected to the general-purpose timer
TRGO output), see
These sources can be combined to have multiple concurrent triggers.
Burst mode is not re-triggerable. In continuous mode, new triggers are ignored until the
burst mode is terminated, while in single-shot mode, the triggers are ignored until the
current burst completion including run periods (HRTIM_BMPER+1 cycles). This is also valid
for software trigger (the software bit is reset by hardware even if it is discarded).
Figure 234
immediately or on the timer period following the event.
876/2083
HRTIM
Table 200
shows how the burst mode is started in response to an external event, either
RM0440 Rev 1
Table 203. In this case, the burst mode idle
clock prescaled by a factor defined with BMPRSC[3:0]
HRTIM
for details.
RM0440
clock cycles long to be