ST STM32G4 Series Reference Manual page 711

RM0440
At the same time, the DAC channel2 triangle counter, with the same triangle amplitude, is
added to the DHR2 register and the sum is transferred into DAC_DOR2 (three dac_hclk
clock cycles later). The DAC channel2 triangle counter is then updated.
Simultaneous trigger with different triangle generation
To configure the DAC in this conversion mode, the following sequence is required:
1. Set the two DAC channel trigger enable bits TEN1 and TEN2
2. Configure the same trigger source for both DAC channels by setting the same value in
the TSEL1 and TSEL2 bitfields.
3. Configure the two DAC channel WAVEx[1:0] bits as 1x and set different maximum
amplitude values in the MAMP1[3:0] and MAMP2[3:0] bits.
4. Load the dual DAC channel data into the desired DHR register (DAC_DHR12RD,
DAC_DHR12LD or DAC_DHR8RD).
When a trigger arrives, the DAC channel1 triangle counter, with a triangle amplitude
configured by MAMP1[3:0], is added to the DHR1 register and the sum is transferred into
DAC_DOR1 (three AHB clock cycles later). Then the DAC channel1 triangle counter is
updated.
At the same time, the DAC channel2 triangle counter, with a triangle amplitude configured
by MAMP2[3:0], is added to the DHR2 register and the sum is transferred into DAC_DOR2
(three dac_hclk clock cycles later). Then the DAC channel2 triangle counter is updated.
Simultaneous trigger with single sawtooth wave generation
To configure the DAC in this conversion mode, the following sequence is required:
1. Configure the same trigger source for both DAC channels by setting the same value in
STRSTTRIGSEL1[3:0],STRSTTRIGSEL2[3:0], STINCTRIGSEL2[3:0] and
STINCTRIGSEL1[3:0] bits.
2. Configure the two DAC channel WAVEx[1:0] bits to 11 and set the same
STRSTDATAx[11:0], STINCDATAx[15:0] and STDIRx value for each register.
When a trigger arrives, the DAC channel1/2 sawtooth counter updates DHR1 and DHR2
registers and loads them into DAC_DOR1/2 (three AHB clock cycles later).
Simultaneous trigger with different sawtooth wave generation
To configure the DAC in this conversion mode, the following sequence is required:
1. Configure the same trigger source for both DAC channels by setting the same value in
STRSTTRIGSEL1[3:0], STRSTTRIGSEL2[3:0], STINCTRIGSEL2[3:0] bits and
STINCTRIGSEL1[3:0] bits.
2. Configure the two DAC channel WAVEx[1:0] bits to 11 and set different
STRSTDATAx[11:0], STINCDATAx[15:0], STDIRx values for each register.
When a trigger arrives, DAC channel1/2 sawtooth counter updates the DHR1 and DHR2
registers and loads them independently into DAC_DOR1/2 (three AHB clock cycles later).
RM0440 Rev 1
Digital-to-analog converter (DAC)
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